Technical Field
The present disclosure relates to a frequency divider and a phase-locked loop including the same.
Description of the Related Art
To synchronize electrical signals between different electronic components, a system clock is commonly used as a timing device to send data or signals between the different components. In particular, a phase-locked loop (PLL) is typically used to establish the system clock.
A PLL typically includes an input reference clock divider (input divider), a phase frequency detector (PFD), a charge pump (CP), a low pass filter (LPF), a voltage controlled oscillator (VCO), and a feedback clock frequency converter (feedback divider). The PLL compares an input reference clock signal (input signal) with an output frequency-divided clock signal (output signal), aligns the phases of the input and output signals, and locks the frequency ratio between the input and output signals (frequency multiple ratio).
The input signal having a particular frequency may be generated from a crystal oscillator or other means. The frequency of the output signal is determined by the PLL. In most instances, the (synthesized) output signal is much faster than the input signal. Thus, the feedback divider is usually operated at high speeds.
Frequency dividers may be classified into synchronous dividers and asynchronous dividers. Asynchronous dividers can be operated in multiple stages. Each stage runs at lower frequency, which results in lower power consumption and reduced high frequency clock loading. However, asynchronous dividers have the disadvantage of jitter/latency accumulation.
Although synchronous dividers have reduced jitter, all flip-flops in the synchronous dividers are operated at maximum frequency, which results in higher power consumption and large loading on the high frequency clock.